The aggressive gate length downscaling in CMOS technology for logical applications may allow that a CMOS transistor could now reach a frequency domain, which was previously reserved for bipolar transistors.
A MOSFET device may be considered to be short when the channel length is in the same order of magnitude as the depletion layer width of the source and drain junction. As the channel length may be reduced to increase both the operation speed and the number of components per chips, so-called short channel effects may arise which implied that the transistors are becoming more and more leaky.
When the depletion region surrounding the drain extends to the source (so that the two depletion layers merge), leakage or punch-through may occur which can be reduced or minimized in different ways like with the use of thinner gate oxide layers, larger substrate doping, shallower junctions, and with a longer channel. The use of raised source/drain is also an efficient way to improve with respect to the short channel effects, because it allows more shallow source/drains. It is also possible to reduce the series resistance of source/drain regions with elevated source/drains. This technique usually requires selective epitaxy growth which is difficult to implement in a production environment.
For the scaling, that is reduction in size, of devices in integrated circuits, all dimensions have to be reduced. As a consequence the junction depth has to be reduced. This reduction of depth should not reduce the conductivity of the source/drain regions from the channel edge to the source/drain contacts. Increasing the doping level of the source/drain areas enhances the conductivity but also enhances the electric field at these junctions including higher leakage and lower breakdown voltages of these junctions. Both latter effects are detrimental for further scaling. Therefore, it is desirable to have a device in which the dimensions are reduced, and simultaneously the doping levels are increased, but on the other hand it is desired to limit the resulting field increase as much as possible.
Curvature of junctions includes high electric fields at these curved junctions: The lower the radius the higher the field. With decreasing dimensions, the radius goes down so the field goes up. If one could avoid or reduce the junction curvature (this lower curvature results in a larger effective radius), the electric field would go up less with the ever increasing doping levels.
Shaping a gradually increasing source/drain extension depth by using a number of implants with varying implant tilts or growing elevated source/drains may remedy the excessive increase of the electric field due to the scaling, but may be expensive. Such a multiple implant method is not only expensive, but may also implant part of the extension through the gate oxide. This may harm the gate oxide integrity. The elevated source/drain by epitaxial growth is not only expensive but also induces extra source/gate, drain/gate and source/drain capacitances which may be problematic for high frequency operation.
U.S. Pat. No. 5,953,615 discloses MOSFETs with deep source/drain junctions and shallow source/drain extensions, and provides on a semiconductor wafer a gate stack with side spacers. The side spacers are etched so that a known thickness of the side spacers is left. An ion beam is used to implant Si+ or Ge+ or Xe+ to amorphize the silicon region, creating an amorphous region with two different depths. A high dose ion beam is then used to implant a dopant. An oxide layer is then deposited as a barrier layer, and then a metal layer is deposited to improve laser energy absorption. Laser annealing is used to melt the amorphous silicon region which causes the dopant to diffuse in and into the amorphous silicon region creating deep source/drain junctions and shallow source/drain extensions. Standard techniques are then used to complete the transistor, which includes silicidation of the source/drain junctions.
However, such transistor manufacture procedures may be cumbersome and expensive.